In the fabrication of semiconductor devices, isolation structures are formed in a wafer substrate between active areas in which electrical devices such as transistors, memory cells, or the like, are to be formed. The substrate is typically lightly doped with p-type dopants, and wells are formed in the upper portions of the active substrate regions. Thereafter, transistors may be formed in and above the wells, where source drain regions are formed in the wells by implantation of opposite dopant types. For example, in twin-well processes, n-wells and p-wells are formed by implanting n and p type dopants, respectively, into appropriate well regions of a lightly p-doped silicon substrate or an epitaxial silicon layer in a silicon-over-insulator (SOI) wafer. PMOS transistors are fabricated in the n-well regions by implanting p-type dopants in the n-wells to form PMOS source/drain terminals. Similarly, NMOS source/drains are formed by implanting n-type dopants into the p-wells.
In the operation of such devices, well to well electrical isolation is important to ensure proper operation of the transistor devices formed in the wells. Local oxidation of silicon (LOCOS) or shallow trench isolation (STI) techniques are commonly employed to form isolation structures between such adjacent wells. However, such isolation structures may not prevent leakage from one well to an adjacent well in all operating conditions. For instance, adjacent, non-contiguous n-wells may be biased differently in device operation, by which a voltage difference exists between the adjacent wells. If the voltage difference is large enough, well to well leakage may result, even where an isolation structure (e.g., LOCOS or STI) is located between the top portions of the wells. Where the well to well isolation is insufficient, the depletion regions in adjacent n-wells may merge together, resulting in undesirable punch-thru conditions and leakage between the adjacent n-wells.
The resistivity of the substrate material between adjacent wells plays an important role in determining the amount or likelihood of well to well leakage for a given biasing condition. In general, lower substrate resistivity (e.g., increased p-type substrate dopant concentration) provides improved isolation because more dopants are available to inhibit depletion region merging. Conversely, higher resistivity substrates (e.g., lower dopant concentration) are more susceptible to punch-thru leakage between adjacent n-wells. Accordingly, many CMOS devices are fabricated using low resistance p-doped silicon substrates, such as having a resistivity on the order of about 2 ohm-cm, to ensure appropriate well to well isolation.
However, certain applications call for higher substrate resistivity, such as in circuits which include RF components. For example, RF inductors may be fabricated in an RF region of a wafer, for which a high quality or “Q” factor is needed. A signal passing through the inductor will tend to induce a current in the substrate, causing a loss. The higher the substrate resistivity, the lower this loss will be. The Q factor is a measure of the amount of loss in the inductor, where a high Q factor indicates low loss. Accordingly, to facilitate manufacture of high Q (e.g., low loss) passive RF components, it is desirable to employ a relatively high resistivity p-doped silicon substrate, such as having a resistivity on the order of about 50 ohm-cm.
In mixed signal devices, both CMOS digital circuits and high frequency RF circuits are provided, wherein the RF components are built in an RF region and digital components are fabricated in other active areas of the wafer. In this situation, a tradeoff is required between low resistance p-doped silicon substrates (e.g., to help well to well isolation in the CMOS circuits) and high resistance substrates (e.g., to provide low loss passive RF components). However, such a tradeoff sacrifices one performance criteria in favor of the other. Accordingly, there remains a need for techniques by which well to well isolation may be improved without significantly impacting low loss passive RF components in a mixed-signal semiconductor device, and without adding significant processing time or expense to the manufacturing process.